README.md

A Router for TinyNet

Why

This is board for switching UART signals in TinyNet. I wanted to keep some track of what I was doing, while I was doing it. So here it is.

Originally, I had developed a switch on the XMEGA platform. I wanted to get into something a bit heavier duty, as I thought a really neat trick would be to out-perform switched ethernet, outright (for network control systems, not for datacenters). I think that in ARM chips there was enough speed to do this. Maximum UART bitrate is a function of the core clock speed (and in this case, the peripheral clock speed). I went straight to the 300MHz ATSAMx70 chips (M7 cores).

Now, being more prudent I would do some tests with these chips first, but I'm not going to. This is foolish, I know that. Max UART on the ATSAMS70 is clk/16, so 18.75Mbps. It's not huge (relative ethernet), but it's fast enough for realtime small messages on small systems. In any case, I think the question is about system architecture more than it is about outright performance at this point.

I also think that, for pure switching, an FPGA or PSOC would be a better answer. It probably is. I want to experiment with those during Networks week in how to make.

However, I also want my network switches to double-duty as motor controllers, sensor interfaces, etc - do general embedded-stuff. In another world, where infinite time exists, I would put FPGAs on board with a processor. With the FPGA comes a chance to invent a whole new PHY - w/ 'co-clocking' and auto-maxing bitrates, which is something I am still really interested in implementing, but there are also machines to build. I leave that experiment for another bench.

The Chip

First order was picking the right Microcontroller for the job. I want a lot of things, and I expect this chip to become the heart of much of the work I'll do during the next two years, so the datasheet stakes have never been so high.

**I want a chip with: **

• 5+ uarts
• Big Clock Speed
• DMA (direct memory access - peripherals write right into memory)
• PWM's
• ADC's
• I2C
• SPI
• PIO (parallel input / output) is really exciting for communication

M7's

I ended up looking through Atmel's M4 and M7 Series of chips. These seem reasonably priced (actually cheap relative STM's). They're ARM, so the toolchain should be friendly to others. The M7's have a 300MHz clock that I'm getting childishly excited about.

My one issue is that they are a bit too fancy, and don't have exactly the peripherals I want. The XMEGAs have like 12 UARTS etc, the M7's max out at 5, even with 144 pins.

I can also tell that programming these is going to be ... well ... less straightforward.

GO FOR

• ATSAME70 - series - or ATSAMS70
• E70 is 'industrial' - and S70 lacks an Ethernet Phy, but seems like it's way more popular...
• oodles of peripherals
• a chip you could drown in
• 300MHz
• did I mention peripherals?
• $8 ... a good middle ground

ATSAMS70N20

• Exact PN ATSAMS70N20A-AN

• N19: 512kb Flash, N20: 1024, N21: 2048

• 300MHz

• OOF: Need S70N-series for USART / SPI (has 100 pins :|)

• Do LQFP for 14.5x14.5mm IC: TFBGA available, is 9x9mm

• Reads the datasheet

• print p. 1 -> 31 pins

• print p. 77 -> 84 debug

• p. 279 -> 346 clock / pmic

• p. 346 -> 421 pio (gpio)

• print p. 1093 -> 1117 uart

• print p. 756 -> 788 spi

• p. 831 -> 835 brief twi (i2c)

• p. 964 - 968 brief usart

• print p. 1178 -> 1186 -> 1282 pwm

• p. 1283 -> 1288 afec (adc) brief

• p. 158 -> 164 Power

• p. 1554 -> 1574 Schematics

• UART max clock is the Peripheral Clock or the PMC PCK - divided by 16. PMC PCK is an external clock, so UART clock can remain independent of processor clock.

• So we can have (as measured) 22.8Mbps UART - into high-speed bouncy signal land. Exciting.

Bonus Breakout