diff --git a/python/pcb.png b/python/pcb.png
index a6c3b584b7c8da9dcd489bd414a42d16089e3472..6ea45400e439267b87373685f5bfb6f72f7f6d60 100644
Binary files a/python/pcb.png and b/python/pcb.png differ
diff --git a/python/pcb.py b/python/pcb.py
index a7b57406aae31fc0bf6c86089530608d8deb9ecd..866c9313388b108692ab84339d5b943cc74faa38 100755
--- a/python/pcb.py
+++ b/python/pcb.py
@@ -21,12 +21,11 @@
#
#output = "top, labels, and exterior"
-output = "top, labels, holes, and exterior"
+#output = "top, labels, holes, and exterior"
#output = "top, bottom, labels, and exterior"
-#output = "top, bottom, labels, holes, and exterior"
+output = "top, bottom, labels, holes, and exterior"
#output = "top traces"
#output = "top traces and exterior"
-#output = "top traces, holes, and exterior"
#output = "bottom traces reversed"
#output = "bottom traces reversed and exterior"
#output = "holes"
@@ -958,6 +957,7 @@ class PCB:
self.exterior = subtract(true,rectangle(x0,x0+width,y0,y0+height))
self.mask = false
self.holes = false
+ self.cutout = false
def add(self,part):
self.board = add(self.board,part)
self.mask = add(self.mask,move(part,-mask,mask))
@@ -1005,6 +1005,16 @@ class part:
elif (angle != 0):
self.holes = rotate(self.holes,angle)
self.holes = translate(self.holes,x,y,z)
+ if hasattr(self,'cutout'):
+ if (angle == 90):
+ self.cutout = rotate_90(self.cutout)
+ elif (angle == 180):
+ self.cutout = rotate_180(self.cutout)
+ elif ((angle == 270) | (angle == -90)):
+ self.cutout = rotate_270(self.cutout)
+ elif (angle != 0):
+ self.cutout = rotate(self.cutout,angle)
+ self.cutout = translate(self.cutout,x,y,z)
deg_angle = angle
angle = math.pi*angle/180
for i in range(len(self.pad)):
@@ -1027,6 +1037,9 @@ class part:
pcb = pcb.add(self.shape)
if hasattr(self,'holes'):
pcb.holes = add(pcb.holes,self.holes)
+ if hasattr(self,'cutout'):
+ pcb.interior = subtract(pcb.interior,self.cutout)
+ pcb.exterior = add(pcb.exterior,self.cutout)
return pcb
def wire(pcb,width,*points):
@@ -1080,7 +1093,6 @@ class via(part):
self.pad.append(point(0,0,zt))
self.pad.append(point(0,0,zb))
-
class SJ(part):
#
# solder jumper
@@ -1176,6 +1188,66 @@ class choke(part):
# connectors
#
+class TFT8x1v(part):
+ #
+ # TFT 8x1 vertical
+ # 2x Sullins S5635-ND
+ #
+ def __init__(self,value=''):
+ pad_header = cube(-.079/2,.079/2,-.039/2,.039/2,0,0)
+ d = .209/2-.079/2
+ self.value = value
+ self.pad = [point(0,0,0)]
+ self.labels = []
+ #
+ # pin 1
+ #
+ self.shape = translate(pad_header,-d,-.35,0)
+ self.pad.append(point(-d,-.35,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'1LED'))
+ #
+ # pin 2
+ #
+ self.shape = add(self.shape,translate(pad_header,d,-.25,0))
+ self.pad.append(point(d,-.25,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'SCK'))
+ #
+ # pin 3
+ #
+ self.shape = add(self.shape,translate(pad_header,-d,-.15,0))
+ self.pad.append(point(-d,-.15,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'MOSI'))
+ #
+ # pin 4
+ #
+ self.shape = add(self.shape,translate(pad_header,d,-.05,0))
+ self.pad.append(point(d,-.05,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'DC'))
+ #
+ # pin 5
+ #
+ self.shape = add(self.shape,translate(pad_header,-d,.05,0))
+ self.pad.append(point(-d,.05,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'RST'))
+ #
+ # pin 6
+ #
+ self.shape = add(self.shape,translate(pad_header,d,.15,0))
+ self.pad.append(point(d,.15,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'CS'))
+ #
+ # pin 7
+ #
+ self.shape = add(self.shape,translate(pad_header,-d,.25,0))
+ self.pad.append(point(-d,.25,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'GND'))
+ #
+ # pin 8
+ #
+ self.shape = add(self.shape,translate(pad_header,d,.35,0))
+ self.pad.append(point(d,.35,0))
+ self.labels.append(self.text(self.pad[-1].x,self.pad[-1].y,self.pad[-1].z,'VCC'))
+
class header_SWD_4_05(part):
#
# 4-pin header
@@ -1329,8 +1401,8 @@ class USB_A_plug(part):
#
# plug cutout
#
- self.holes = cube(-.05,1,.24,1,zb,zt)
- self.holes = add(self.holes,cube(-.05,1,-1,-.24,zb,zt))
+ self.cutout = cube(-.05,1,.24,1,zb,zt)
+ self.cutout = add(self.cutout,cube(-.05,1,-1,-.24,zb,zt))
class header_SWD(part):
#
@@ -6576,11 +6648,11 @@ pcb = PCB(x,y,width,height,mask)
IC1 = ATtiny44_SOICN('IC1\nt44')
pcb = IC1.add(pcb,x+.49,y+.56)
-VIC1 = via(zb,zt,rv,rp)
-pcb = VIC1.add(pcb,IC1.pad[14].x+.08,IC1.pad[14].y+.02)
+V1 = via(zb,zt,rv,rp,'V1')
+pcb = V1.add(pcb,IC1.pad[14].x+.08,IC1.pad[14].y+.02)
pcb = wire(pcb,w,
- VIC1.pad[1],
+ V1.pad[1],
IC1.pad[14])
J1 = header_ISP('J1\nISP')
@@ -6608,23 +6680,23 @@ pcb = wire(pcb,w,
point(J1.pad[5].x,IC1.pad[4].y),
J1.pad[5])
-VJ12 = via(zb,zt,rv,rp)
-pcb = VJ12.add(pcb,J1.pad[2].x+.075,J1.pad[2].y)
+V2 = via(zb,zt,rv,rp,'V2')
+pcb = V2.add(pcb,J1.pad[2].x+.075,J1.pad[2].y)
pcb = wire(pcb,w,
- VJ12.pad[1],
+ V2.pad[1],
J1.pad[2])
-VJ16 = via(zb,zt,rv,rp)
-pcb = VJ16.add(pcb,J1.pad[6].x-.075,J1.pad[6].y)
+V3 = via(zb,zt,rv,rp,'V3')
+pcb = V3.add(pcb,J1.pad[6].x-.075,J1.pad[6].y)
pcb = wire(pcb,w,
- VJ16.pad[1],
+ V3.pad[1],
J1.pad[6])
pcb = wire(pcb,w,
- VJ16.pad[2],
- VIC1.pad[2])
+ V3.pad[2],
+ V1.pad[2])
J2 = header_FTDI('J2 FTDI')
pcb = J2.add(pcb,x+width-.22,IC1.y-.0,angle=0)
@@ -6642,16 +6714,16 @@ pcb = wire(pcb,w,
point(IC1.pad[12].x+.11,J2.pad[5].y),
J2.pad[5])
-VJ2 = via(zb,zt,rv,rp)
-pcb = VJ2.add(pcb,J2.pad[3].x+.1,J2.pad[3].y)
+V4 = via(zb,zt,rv,rp,'V4')
+pcb = V4.add(pcb,J2.pad[3].x+.1,J2.pad[3].y)
pcb = wire(pcb,w,
- VJ2.pad[1],
+ V4.pad[1],
J2.pad[3])
pcb = wire(pcb,w,
- VJ12.pad[2],
- VJ2.pad[2])
+ V2.pad[2],
+ V4.pad[2])
XTAL1 = XTAL_EFOBM('XTAL1\n20 MHz')
pcb = XTAL1.add(pcb,IC1.pad[4].x-.2,IC1.pad[13].y+.003,angle=-90)
@@ -6666,16 +6738,16 @@ pcb = wire(pcb,w,
IC1.pad[3],
XTAL1.pad[3])
-VXTAL = via(zb,zt,rv,rp)
-pcb = VXTAL.add(pcb,XTAL1.x-.12,XTAL1.y)
+V5 = via(zb,zt,rv,rp,'V5')
+pcb = V5.add(pcb,XTAL1.x-.12,XTAL1.y)
pcb = wire(pcb,w,
XTAL1.pad[2],
- VXTAL.pad[1])
+ V5.pad[1])
pcb = wire(pcb,w,
- VJ16.pad[2],
- VXTAL.pad[2])
+ V3.pad[2],
+ V5.pad[2])
R1 = R_1206('R1\n10k');
pcb = R1.add(pcb,IC1.pad[1].x,IC1.pad[1].y+.1)
@@ -6689,17 +6761,17 @@ pcb = wire(pcb,w,
point(J1.pad[5].x,R1.y),
J1.pad[5])
-VR1 = via(zb,zt,rv,rp)
-pcb = VR1.add(pcb,R1.pad[1].x-.08,R1.y)
+V6 = via(zb,zt,rv,rp,'V6')
+pcb = V6.add(pcb,R1.pad[1].x-.08,R1.y)
pcb = wire(pcb,w,
- VR1.pad[1],
+ V6.pad[1],
R1.pad[1])
pcb = wire(pcb,w,
- VJ2.pad[2],
- point(VJ2.x,VR1.y,zb),
- VR1.pad[2])
+ V4.pad[2],
+ point(V4.x,V6.y,zb),
+ V6.pad[2])
C1 = C_1206('C1\n1uF');
pcb = C1.add(pcb,IC1.pad[14].x,R1.y)
@@ -6710,19 +6782,19 @@ pcb = wire(pcb,w,
pcb = wire(pcb,w,
C1.pad[2],
- VIC1.pad[1])
+ V1.pad[1])
-VC1 = via(zb,zt,rv,rp)
-pcb = VC1.add(pcb,C1.pad[1].x-.025,C1.y-.06)
+V7 = via(zb,zt,rv,rp,'V7')
+pcb = V7.add(pcb,C1.pad[1].x-.025,C1.y-.06)
pcb = wire(pcb,w,
- VC1.pad[1],
+ V7.pad[1],
C1.pad[1])
pcb = wire(pcb,w,
- VR1.pad[2],
- point(VC1.x,VR1.y,zb),
- VC1.pad[2])
+ V6.pad[2],
+ point(V7.x,V6.y,zb),
+ V7.pad[2])
#
# select output
@@ -6735,16 +6807,15 @@ if (output == "top, labels, and exterior"):
outputs["layers"] = [zt]
elif (output == "top, labels, holes, and exterior"):
outputs["function"] = add(add(color(Tan,pcb.board),pcb.labels),
- color(White,add(pcb.exterior,pcb.holes)))
+ add(color(White,pcb.exterior),color(Blue,pcb.holes)))
outputs["layers"] = [zt]
elif (output == "top, bottom, labels, and exterior"):
outputs["function"] = add(add(color(Tan,pcb.board),pcb.labels),
color(White,pcb.exterior))
outputs["layers"] = [zb,zt]
elif (output == "top, bottom, labels, holes, and exterior"):
- outputs["function"] = add(add(color(Tan,
- subtract(pcb.board,pcb.holes)),pcb.labels),
- color(White,pcb.exterior))
+ outputs["function"] = add(add(color(Tan,pcb.board),pcb.labels),
+ add(color(White,pcb.exterior),color(Blue,pcb.holes)))
outputs["layers"] = [zb,zt]
elif (output == "top traces"):
outputs["function"] = color(White,pcb.board)
@@ -6752,10 +6823,6 @@ elif (output == "top traces"):
elif (output == "top traces and exterior"):
outputs["function"] = color(White,add(pcb.board,pcb.exterior))
outputs["layers"] = [zt]
-elif (output == "top traces, holes, and exterior"):
- outputs["function"] = color(White,
- add(add(pcb.board,pcb.exterior),pcb.holes))
- outputs["layers"] = [zt]
elif (output == "bottom traces reversed"):
outputs["function"] = color(White,
reflect_x(pcb.board,2*x+width))