flash/nor: Add Ambiq Micro Apollo flash driver.

Initial release of Ambiq Micro Apollo flash driver
supporting our sub-threshold (low power) Cortex M4F part,
and Evaluation Kit.

We have been shipping openocd to our customers for about one year.

The EVK boards are SWD only using ftdi. We also use two of the
other COM instances to display debug information.

It takes about 15 seconds to flash 512K, and mass erase is
about 5 seconds.

Tested by internal verification group, FAE's, and customer sites.

Merged commit 'refs/changes/17/3417/1' as suggested. Makefile.am
and drivers.c follow the new format to avoid conflicts.

Removed unused fault_capture command.

Added documentation for flash driver.

Change-Id: Iae92d869369c6827244f0071f9cb522d8d91fed8
Signed-off-by: Rick Foos <rfoos@solengtech.com>
Reviewed-on: http://openocd.zylin.com/3230


Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

doc/openocd.texi

@@ -4960,6 +4960,52 @@ flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
+@deffn {Flash Driver} ambiqmicro
+@cindex ambiqmicro
+@cindex apollo
+All members of the Apollo microcontroller family from
+Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
+The host connects over USB to an FTDI interface that communicates
+with the target using SWD.
+
+The @var{ambiqmicro} driver reads the Chip Information Register detect
+the device class of the MCU.
+The Flash and Sram sizes directly follow device class, and are used
+to set up the flash banks.
+If this fails, the driver will use default values set to the minimum
+sizes of an Apollo chip.
+
+All Apollo chips have two flash banks of the same size.
+In all cases the first flash bank starts at location 0,
+and the second bank starts after the first.
+
+@example
+# Flash bank 0
+flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
+# Flash bank 1 - same size as bank0, starts after bank 0.
+flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 $_TARGETNAME
+@end example
+
+Flash is programmed using custom entry points into the bootloader.
+This is the only way to program the flash as no flash control registers
+are available to the user.
+
+The @var{ambiqmicro} driver adds some additional commands:
+
+@deffn Command {ambiqmicro mass_erase} <bank>
+Erase entire bank.
+@end deffn
+@deffn Command {ambiqmicro page_erase} <bank> <first> <last>
+Erase device pages.
+@end deffn
+@deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
+Program OTP is a one time operation to create write protected flash.
+The user writes sectors to sram starting at 0x10000010.
+Program OTP will write these sectors from sram to flash, and write protect
+the flash.
+@end deffn
+@end deffn
+
 @anchor{at91samd}
 @deffn {Flash Driver} at91samd
 @cindex at91samd

src/flash/nor/Makefile.am

@@ -10,6 +10,7 @@ libocdflashnor_la_SOURCES = \
 NOR_DRIVERS = \
 	aduc702x.c \
 	aducm360.c \
+	ambiqmicro.c \
 	at91sam4.c \
 	at91sam4l.c \
 	at91samd.c \

src/flash/nor/drivers.c

@@ -24,6 +24,7 @@
 
 extern struct flash_driver aduc702x_flash;
 extern struct flash_driver aducm360_flash;
+extern struct flash_driver ambiqmicro_flash;
 extern struct flash_driver at91sam3_flash;
 extern struct flash_driver at91sam4_flash;
 extern struct flash_driver at91sam4l_flash;
@@ -75,6 +76,7 @@ extern struct flash_driver xmc4xxx_flash;
 static struct flash_driver *flash_drivers[] = {
 	&aduc702x_flash,
 	&aducm360_flash,
+	&ambiqmicro_flash,
 	&at91sam3_flash,
 	&at91sam4_flash,
 	&at91sam4l_flash,