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flash/nor/kinetis: pull SRST low during mass erase
Mass erase operation might be impacted by different factors, apparently the most reliable way is to do it while asserting the chip reset line. Change-Id: Id6ab57eaec86e402ffdf4f5c8843e7735640f03e Signed-off-by:Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2424 Tested-by: jenkins Reviewed-by:
Spencer Oliver <spen@spen-soft.co.uk>
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