AM335x: Disable watchdog on 'reset halt'

At least on my (phyCORE-AM335X) system, the AM335x watchdog
needs to be disabled to use OpenOCD for more than 6.5 seconds
after reset.

Change-Id: I3d883a9f572b0ccb92f9864853a00c372e39d7f2
Signed-off-by: Harald Welte <laforge@gnumonks.org>
Reviewed-on: http://openocd.zylin.com/3391


Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

tcl/target/am335x.cfg

@@ -76,3 +76,35 @@ target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80
 
 # SRAM: 64K at 0x4030.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
+
+
+# when putting the target into 'reset halt', we need to disable the watchdog as
+# it would otherwise trigger while we're in JTAG
+# FIXME: unify with target/am437x.cfg
+source [find mem_helper.tcl]
+set  WDT1_BASE_ADDR                  0x44e35000
+set  WDT1_W_PEND_WSPR                [expr       $WDT1_BASE_ADDR     +  0x0034]
+set  WDT1_WSPR                       [expr       $WDT1_BASE_ADDR     +  0x0048]
+proc disable_watchdog { } {
+	global WDT1_WSPR
+	global WDT1_W_PEND_WSPR
+	global _TARGETNAME
+
+	set curstate [$_TARGETNAME curstate]
+
+	if { [string compare $curstate halted] == 0 } {
+		set WDT_DISABLE_SEQ1	0xaaaa
+		set WDT_DISABLE_SEQ2	0x5555
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
+
+		# Empty body to make sure this executes as fast as possible.
+		# We don't want any delays here otherwise romcode might start
+		# executing and end up changing state of certain IPs.
+		while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+
+		mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
+		while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+	}
+}
+$_TARGETNAME configure -event reset-end { disable_watchdog }