Added asser_reset and deassert_reset for cortex_a8

git-svn-id: svn://svn.berlios.de/openocd/trunk@2791 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/cortex_a8.c

@@ -67,6 +67,8 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
 		uint32_t *value, int regnum);
 int cortex_a8_dap_write_coreregister_u32(target_t *target,
 		uint32_t value, int regnum);
+int cortex_a8_assert_reset(target_t *target);
+int cortex_a8_deassert_reset(target_t *target);
 
 target_type_t cortexa8_target =
 {
@@ -140,6 +142,11 @@ int cortex_a8_init_debug_access(target_t *target)
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
 	/* Enabling of instruction execution in debug mode is done in debug_entry code */ 
 	
+	/* Resync breakpoint registers */
+	
+	/* Since this is likley called from init or reset, update targtet state information*/
+	cortex_a8_poll(target);
+	
 	return retval;
 }
 
@@ -1188,6 +1195,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
  * Cortex-A8 Reset fuctions
  */
 
+int cortex_a8_assert_reset(target_t *target)
+{
+
+	LOG_DEBUG(" ");
+
+	/* registers are now invalid */
+	armv4_5_invalidate_core_regs(target);
+
+	target->state = TARGET_RESET;
+	
+	return ERROR_OK;
+}
+
+int cortex_a8_deassert_reset(target_t *target)
+{
+
+	LOG_DEBUG(" ");
+
+	if (target->reset_halt)
+	{
+		int retval;
+		if ((retval = target_halt(target)) != ERROR_OK)
+			return retval;
+	}
+
+	return ERROR_OK;
+}
 
 /*
  * Cortex-A8 Memory access