STM32L: Added flash driver and target

Added the flash driver for the STM32L family, which highly differ from the STM32F family.
Added the TCL target file for JTAG access.

contrib/loaders/flash/stm32lx.S

+/***************************************************************************
+ *   Copyright (C) 2010 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   Copyright (C) 2011 Øyvind Harboe                                      *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
+ *   Copyright (C) 2011 Clement Burin des Roziers                          *
+ *   clement.burin-des-roziers@hikob.com                                   *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+
+// Build : arm-eabi-gcc -c stm32lx.S
+	.text
+	.syntax unified
+	.cpu cortex-m3
+	.thumb
+	.thumb_func
+	.global write
+
+/*
+	r0 - destination address
+	r1 - source address
+	r2 - count
+*/
+
+	// Set 0 to r3
+	movs	r3, #0
+	// Go to compare
+	b.n test_done
+
+write_word:
+	// Load one word from address in r0, increment by 4
+	ldr.w	ip, [r1], #4
+	// Store the word to address in r1, increment by 4
+	str.w	ip, [r0], #4
+	// Increment r3
+	adds	r3, #1
+
+test_done:
+	// Compare r3 and r2
+	cmp 	r3, r2
+	// Loop if not zero
+	bcc.n	write_word
+
+	// Set breakpoint to exit
+	bkpt	#0x00
+

src/flash/nor/Makefile.am

@@ -26,6 +26,7 @@ NOR_DRIVERS = \
 	stellaris.c \
 	stm32f1x.c \
 	stm32f2x.c \
+	stm32lx.c \
 	str7x.c \
 	str9x.c \
 	str9xpec.c \

src/flash/nor/drivers.c

@@ -34,6 +34,7 @@ extern struct flash_driver stellaris_flash;
 extern struct flash_driver str9xpec_flash;
 extern struct flash_driver stm32f1x_flash;
 extern struct flash_driver stm32f2x_flash;
+extern struct flash_driver stm32lx_flash;
 extern struct flash_driver tms470_flash;
 extern struct flash_driver ecosflash_flash;
 extern struct flash_driver ocl_flash;
@@ -65,6 +66,7 @@ static struct flash_driver *flash_drivers[] = {
 	&str9xpec_flash,
 	&stm32f1x_flash,
 	&stm32f2x_flash,
+	&stm32lx_flash,
 	&tms470_flash,
 	&ecosflash_flash,
 	&ocl_flash,

tcl/target/stm32l.cfg

+# script for stm32l
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32l
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 14kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x3800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
+adapter_khz 100
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0038
+  # Section 24.6.3
+   set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0038
+  # Section 24.6.2
+  set _BSTAPID 0x06416041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
+
+proc stm32l_enable_HSI {} {
+	# Enable HSI as clock source
+	echo "STM32L: Enabling HSI"
+	
+	# Set HSION in RCC_CR
+	mww 0x40023800 0x00000101
+	
+	# Set HSI as SYSCLK
+	mww 0x40023808 0x00000001
+	
+	# Increase JTAG speed
+	adapter_khz 2000
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l_enable_HSI
+}
+