.gitignore

+**.l#*
\ No newline at end of file

README.md

+These are historical; current library development is at https://gitlab.fabcloud.org/pub/libraries

eagle/README.md

+## Use Fab Design Rules in Eagle
+
+This will help you make sure that traces are not too close together!
+
+In this folder, find ``` fabcity-designrules.dru ```
+
+In Eagle, in the Board Window, find ``` edit >> design rules ``` 
+
+On the first tab, use 'load' and load this .dru file.
+
+Now you can use the 'DRC' command to check!
+
+## Automate the generation of trace.png and cutout.png files
+Matt Keeter wrote a Python script that opens up Eagle and exports a number of pngs using ImageMagick.
+
+To get this script to run, use the following steps:
+* Save eagle_png.py into the folder where you keep your Eagle project folders containing .brd and .sch files
+* Install [ImageMagick](https://www.imagemagick.org/script/index.php)
+* Create a polygon over your .brd design on the Milling layer (number 46)
+* Set the isolate value for the polygon to a number greater than 16, this will ensure there's enough black space for mods to generate toolpaths in (see image below)
+* Save your .brd file and close Eagle
+* Run eagle_png using the following command `python eagle_png.py board_folder/board_name.brd`
+* The script should have saved several .png files into the folder where the .brd file is
+
+<img src="img/isolate.png" alt="Increase isolate value for polygon" width="700"/>
+
+
+> **Note:** With later versions of Eagle (9.0.1+), by default it is configured to show text similar to "1-16" ontop of each via. This comes through even when exporting your final image. To remove this artifact, type the following in the commandline: `SET Option.ViaLength 0`

eagle/eagle_png.py

+#!/usr/bin/env python
+
+import os
+import sys
+import platform
+import glob
+import subprocess
+import hashlib
+
+def find_eagle():
+    if platform.uname()[0] == 'Darwin':
+        try:
+            eagle_dir = glob.glob('/Applications/EAGLE*')[-1]
+        except IndexError:
+            sys.stderr.write("Error: EAGLE not found.\n")
+            sys.exit(1)
+
+        return eagle_dir + '/EAGLE.app/Contents/MacOS/EAGLE'
+    else:
+        if subprocess.call(['which','eagle'],
+                           stdout = open(os.devnull, 'w')):
+            sys.stderr.write("Error: EAGLE not found.\n")
+            sys.exit(1)
+        return 'eagle'
+
+def create_images(name, resolution = 1500):
+    for img in ['top','bottom','cutout','holes','vias']:
+        file = '%s.%s.png' % (name, img)
+        if os.path.isfile(file):
+            os.remove(file)
+
+    script = '''
+ratsnest; write;
+set palette black; window;
+display none top vias pads;
+export image '{name}.top.png' monochrome {resolution};
+display none bottom vias pads;
+export image '{name}.bottom.png' monochrome {resolution};
+display none milling;
+export image '{name}.cutout.png' monochrome {resolution};
+display none holes;
+export image '{name}.holes.png' monochrome {resolution};
+display none vias pads;
+export image '{name}.vias.png' monochrome {resolution};
+quit'''.format(name = name, resolution = resolution)
+    subprocess.call([find_eagle(), '-C', script, name + '.brd'])
+
+def md5(filename):
+    with open(filename,'rb') as f:
+        m = hashlib.md5()
+        for chunk in iter(lambda: f.read(m.block_size*128), ''):
+            m.update(chunk)
+    return m.digest()
+
+def clean_up(name):
+    preserve = ['top','bottom','cutout']
+    for img in ['top','bottom','cutout','holes','vias']:
+        file = '%s.%s.png'   % (name, img)
+        file_ = '%s.%s_.png' % (name, img)
+        if os.path.isfile(file) and img not in preserve:
+            os.remove(file)
+        if os.path.isfile(file_):
+            os.remove(file_)
+
+def print_help():
+    print """command line: eagle_png [options] target.brd
+   target.brd = EAGLE brd file to render
+   The board outline should be a solid polygon on the 'milling' layer
+   Internal cutouts should be solid shapes on the 'holes' layer
+
+   Valid options:
+       --resolution NUM : sets output image resolution
+       --doublesided : forces double-sided mode"""
+    sys.exit(1)
+
+if __name__ == '__main__':
+    if len(sys.argv) == 1:
+        print_help()
+        sys.exit(1)
+
+    # Parse arguments
+    sys.argv = sys.argv[1:]
+    resolution = 1500
+    force_doublesided = False
+
+    while sys.argv:
+        if sys.argv[0] == '--resolution':
+            try:
+                resolution = sys.argv[1]
+                sys.argv = sys.argv[2:]
+            except IndexError:
+                sys.stderr.write("Error: No resolution provided.\n")
+                sys.exit(1)
+            try:
+                resolution = int(resolution)
+            except ValueError:
+                sys.stderr.write("Error: Invalid resolution.\n")
+                sys.exit(1)
+
+        elif sys.argv[0] == '--doublesided':
+            force_doublesided = True
+            sys.argv = sys.argv[1:]
+
+        elif len(sys.argv) == 1:
+            break
+    else:
+        sys.stderr.write("Error: No filename provided.\n")
+        sys.exit(1)
+
+    name = sys.argv[0].replace('.brd','')
+    if not os.path.isfile(name+'.brd'):
+        sys.stderr.write("Error: .brd file does not exist.\n")
+        sys.exit(1)
+
+    vias    = name + '.vias.png'
+    cutout  = name + '.cutout.png'
+    top     = name + '.top.png'
+    bottom  = name + '.bottom.png'
+    holes   = name + '.holes.png'
+
+    print "Rendering images."
+    create_images(name, resolution)
+
+    # Check to make sure that imagemagick is installed.
+    if subprocess.call(['which','convert'], stdout = open(os.devnull, 'w')):
+        sys.stderr.write("""Error: 'convert' not found.
+ImageMagick command-line tools must be installed to use eagle_png.""")
+        sys.exit(1)
+
+    print "Processing images."
+
+    # The following command is a set of ImageMagick instructions that
+    # combine all of the images.
+
+    # The following steps take place:
+    #   - Perform a white flood fill on the vias image, starting in the upper
+    #       left corner.  This makes the via image a set of black holes on
+    #       a uniform white background
+    #   - Multiply the vias and cutout images, to cut the via holes from
+    #       the cutout region.
+    #   - Invert the cutout image.
+    #   - Lighten the top and bottom traces with the inverted cutout.  This
+    #       ensures that we don't waste time milling traces in regions that
+    #       will be cut out of the PCB.
+    #   - Subtract the holes image from the original cutout image
+    #   - Save this combined cutout image
+
+    command = [ 'convert',
+                vias, '-fill', 'white', '-draw', 'color 0,0 floodfill',
+                cutout, '-compose', 'Darken', '-composite',
+                '-compose','Lighten',
+                '(',
+                    '+clone',
+                    '-negate'
+              ]
+
+    # If this is a two-sided board, then process the bottom layer
+    if md5(bottom) != md5(vias) or force_doublesided:
+        command += [
+                    '(',
+                        '+clone', bottom, '-composite',
+                        '-flop', '-write', bottom, '+delete',
+                    ')'
+                    ]
+    else:
+        os.remove(bottom)
+
+    # Process the top layer
+    command += [
+                top, '-composite', '-write', top,
+                    '+delete',
+                ')',
+                holes,  '-compose', 'Minus_Src', '-composite', cutout
+                ]
+
+    # Execute this whole mess
+    subprocess.call(command)
+
+    os.remove(vias)
+    os.remove(holes)
+
+    if bottom in command:
+        print "Generated %s, %s, %s." % (top, bottom, cutout)
+    else:
+        print "Generated %s, %s." % (top, cutout)

eagle/fabcity-designrules.dru

+description[de] = <b>EAGLE Design Rules</b>\n<p>\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
+description[en] = <b>EAGLE Design Rules</b>\n<p>\nThe default Design Rules have been set to cover\na wide range of applications. Your particular design\nmay have different requirements, so please make the\nnecessary adjustments and save your customized\ndesign rules under a new name.
+layerSetup = (1*16)
+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
+mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
+mdWireWire = 16mil
+mdWirePad = 16mil
+mdWireVia = 16mil
+mdPadPad = 16mil
+mdPadVia = 16mil
+mdViaVia = 16mil
+mdSmdPad = 6mil
+mdSmdVia = 6mil
+mdSmdSmd = 6mil
+mdViaViaSameLayer = 6mil
+mnLayersViaInSmd = 2
+mdCopperDimension = 16mil
+mdDrill = 16mil
+mdSmdStop = 0mil
+msWidth = 10mil
+msDrill = 32mil
+msMicroVia = 9.99mm
+msBlindViaRatio = 0.500000
+rvPadTop = 0.250000
+rvPadInner = 0.250000
+rvPadBottom = 0.250000
+rvViaOuter = 0.250000
+rvViaInner = 0.250000
+rvMicroViaOuter = 0.250000
+rvMicroViaInner = 0.250000
+rlMinPadTop = 10mil
+rlMaxPadTop = 20mil
+rlMinPadInner = 10mil
+rlMaxPadInner = 20mil
+rlMinPadBottom = 10mil
+rlMaxPadBottom = 20mil
+rlMinViaOuter = 8mil
+rlMaxViaOuter = 20mil
+rlMinViaInner = 8mil
+rlMaxViaInner = 20mil
+rlMinMicroViaOuter = 4mil
+rlMaxMicroViaOuter = 20mil
+rlMinMicroViaInner = 4mil
+rlMaxMicroViaInner = 20mil
+psTop = -1
+psBottom = -1
+psFirst = -1
+psElongationLong = 100
+psElongationOffset = 100
+mvStopFrame = 1.000000
+mvCreamFrame = 0.000000
+mlMinStopFrame = 4mil
+mlMaxStopFrame = 4mil
+mlMinCreamFrame = 0mil
+mlMaxCreamFrame = 0mil
+mlViaStopLimit = 0mil
+srRoundness = 0.000000
+srMinRoundness = 0mil
+srMaxRoundness = 0mil
+slThermalIsolate = 16mil
+slThermalsForVias = 0
+dpMaxLengthDifference = 10mm
+dpGapFactor = 2.500000
+checkAngle = 0
+checkFont = 1
+checkRestrict = 1
+checkStop = 0
+checkValues = 0
+checkNames = 1
+checkWireStubs = 1
+checkPolygonWidth = 0
+useDiameter = 13
+maxErrors = 50

index.html

@@ -19,12 +19,20 @@ This repository holds libraries of components commonly used in fab classes and l
 
 <div style="margin-left:5%;margin-right:5%;">
 
-<b><a href=https://www.autodesk.com/products/eagle>Eagle</a>:</b> <a href="eagle/fab.lbr">fab.lbr</a>
+<b><a href=https://gitlab.cba.mit.edu/pub/libraries/tree/master/eagle>Eagle</a></b>
 
 <p>
 
-<b><a href=http://kicad-pcb.org>KiCad</a>:</b> <a href="kicad/fab.mod">fab.mod</a> <a href="kicad/fab.lib">fab.lib</a>
+<b><a href=https://gitlab.cba.mit.edu/pub/libraries/tree/master/kicad>KiCad</a></b>
 
 <p>
 
-<b><a href=http://kokompe.cba.mit.edu>Kokompe</a>:</b> <a href=kokompe/pcb.cad>pcb.cad</a>
+<b><a href=https://gitlab.cba.mit.edu/pub/libraries/tree/master/kokompe>Kokompe</a></b>
+
+<p>
+
+<b><a href=https://gitlab.cba.mit.edu/pub/libraries/tree/master/kokopelli>Kokopelli</a></b>
+
+<p>
+
+<b><a href=https://gitlab.cba.mit.edu/pub/libraries/tree/master/python>Python</a></b>

kicad/README.md

+See: https://gitlab.fabcloud.org/pub/libraries/electronics/kicad
+
+## Fab KiCad Footprint Library
+
+Updated and cleaned up 10/15/2020 by zfredin to fix errors and reflect the [homelab inventory](https://gitlab.cba.mit.edu/zfredin/homelab/-/blob/master/components.md); prior footprints to /archive.
+
+![footprints](footprints.png)
+
+### naming convention
+fab_x_y_z.kicad_mod
+
+_x_ is category: C, CONN, IC, LED, R, SMD (for generic footprints), etc
+
+_y_ is size/config: 1x06 (single-row 6-pin header connector), SOIC8 (small outline integrated circuit, 8-pin), etc
+
+_z_ is an optional descriptor, such as "SMD" for connectors to differentiate from thru-hole versions
+
+### general design strategy
+- hand-solderable (i.e., pads should be a bit longer than those intended for automated assembly and reflow soldering)
+- route-able using a 1/64" (~0.4 mm) end mill
+- maximize bridge span (i.e., space to run two tracks under a 1206 component)
+- centered at 0,0
+- component outline, reference, and value on F.Silk layer

kicad/archive/fab.pretty/fab-1X06SMD.kicad_mod

+(module fab-1X06SMD (layer F.Cu) (tedit 200000)
+  (attr smd)
+  (fp_text reference >NAME (at -2.54 0 90) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value "" (at 0 0) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.15)))
+  )
+  (pad 1 smd rect (at 0 -6.35) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 2 smd rect (at 0 -3.81) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 3 smd rect (at 0 -1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 4 smd rect (at 0 1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 5 smd rect (at 0 3.81) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 6 smd rect (at 0 6.35) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+)

kicad/archive/fab.pretty/fab-2-SMD-5X3MM.kicad_mod

+(module fab-2-SMD-5X3MM (layer F.Cu) (tedit 200000)
+  (attr smd)
+  (fp_text reference >NAME (at 0.635 -3.175) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value >VALUE (at 1.27 3.175) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_line (start -2.49936 -1.29794) (end -2.49936 -1.59766) (layer B.SilkS) (width 0.127))
+  (fp_line (start -2.49936 -1.59766) (end 2.49936 -1.59766) (layer B.SilkS) (width 0.127))
+  (fp_line (start 2.49936 -1.59766) (end 2.49936 -1.29794) (layer B.SilkS) (width 0.127))
+  (fp_line (start 2.49936 1.29794) (end 2.49936 1.59766) (layer B.SilkS) (width 0.127))
+  (fp_line (start 2.49936 1.59766) (end -2.49936 1.59766) (layer B.SilkS) (width 0.127))
+  (fp_line (start -2.49936 1.59766) (end -2.49936 1.29794) (layer B.SilkS) (width 0.127))
+  (pad P$1 smd rect (at -1.99898 0) (size 1.99898 2.39776) (layers F.Cu F.Paste F.Mask))
+  (pad P$2 smd rect (at 1.99898 0) (size 1.99898 2.39776) (layers F.Cu F.Paste F.Mask))
+)

kicad/archive/fab.pretty/fab-2X02SMD.kicad_mod

+(module fab-2X02SMD (layer F.Cu) (tedit 200000)
+  (attr smd)
+  (fp_text reference >NAME (at -0.635 -3.175) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value >VALUE (at 0 3.175) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (pad 1 smd rect (at -2.54 -1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 2 smd rect (at 2.91846 -1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 3 smd rect (at -2.54 1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 4 smd rect (at 2.91846 1.27) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+)

kicad/archive/fab.pretty/fab-2X03.kicad_mod

+(module fab-2X03 (layer F.Cu) (tedit 200000)
+  (descr "PIN HEADER")
+  (tags "PIN HEADER")
+  (attr virtual)
+  (fp_text reference >NAME (at -0.635 -3.81) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.127)))
+  )
+  (fp_text value >VALUE (at 0 3.81) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_line (start -2.794 1.524) (end -2.286 1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.286 1.524) (end -2.286 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.794 1.016) (end -2.286 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.794 1.524) (end -2.794 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.794 -1.016) (end -2.286 -1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.286 -1.016) (end -2.286 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.794 -1.524) (end -2.286 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -2.794 -1.016) (end -2.794 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 -1.016) (end 0.254 -1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 0.254 -1.016) (end 0.254 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 -1.524) (end 0.254 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 -1.016) (end -0.254 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 1.524) (end 0.254 1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 0.254 1.524) (end 0.254 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 1.016) (end 0.254 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -0.254 1.524) (end -0.254 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 -1.016) (end 2.794 -1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.794 -1.016) (end 2.794 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 -1.524) (end 2.794 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 -1.016) (end 2.286 -1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 1.524) (end 2.794 1.524) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.794 1.524) (end 2.794 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 1.016) (end 2.794 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start 2.286 1.524) (end 2.286 1.016) (layer F.SilkS) (width 0.06604))
+  (fp_line (start -3.81 1.905) (end -3.175 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -1.905 2.54) (end -1.27 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -1.27 1.905) (end -0.635 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 0.635 2.54) (end 1.27 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -3.81 1.905) (end -3.81 -1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -3.81 -1.905) (end -3.175 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -3.175 -2.54) (end -1.905 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -1.905 -2.54) (end -1.27 -1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -1.27 -1.905) (end -0.635 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -0.635 -2.54) (end 0.635 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 0.635 -2.54) (end 1.27 -1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -1.27 -1.905) (end -1.27 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 1.27 -1.905) (end 1.27 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -0.635 2.54) (end 0.635 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -3.175 2.54) (end -1.905 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 1.27 1.905) (end 1.905 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 3.175 2.54) (end 3.81 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 1.27 -1.905) (end 1.905 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 1.905 -2.54) (end 3.175 -2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 3.175 -2.54) (end 3.81 -1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 3.81 -1.905) (end 3.81 1.905) (layer B.SilkS) (width 0.1524))
+  (fp_line (start 1.905 2.54) (end 3.175 2.54) (layer B.SilkS) (width 0.1524))
+  (fp_line (start -3.175 2.921) (end -1.905 2.921) (layer B.SilkS) (width 0.127))
+  (fp_text user 1 (at -4.445 1.905) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (pad 1 thru_hole rect (at -2.54 1.27) (size 1.524 1.524) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.524 3.048) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 3 thru_hole circle (at 0 1.27) (size 1.524 3.048) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 4 thru_hole circle (at 0 -1.27) (size 1.524 3.048) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 5 thru_hole circle (at 2.54 1.27) (size 1.524 3.048) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.524 3.048) (drill 1.016) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+)

kicad/archive/fab.pretty/fab-2X03SMD.kicad_mod

+(module fab-2X03SMD (layer F.Cu) (tedit 5DC0ADA4)
+  (attr smd)
+  (fp_text reference >NAME (at -0.635 -4.445) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value >VALUE (at 0 4.445) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (pad 1 smd rect (at -2.54 -2.54) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+  (pad 2 smd rect (at 2.91846 -2.54) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+  (pad 3 smd rect (at -2.54 0) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+  (pad 4 smd rect (at 2.91846 0) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+  (pad 5 smd rect (at -2.54 2.54) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+  (pad 6 smd rect (at 2.91846 2.54) (size 2.54 1) (layers F.Cu F.Paste F.Mask))
+)

kicad/archive/fab.pretty/fab-2X04_THRU.kicad_mod

+(module fab-2X04_THRU (layer F.Cu) (tedit 200000)
+  (descr "2X4 HEADER.")
+  (tags "2X4 HEADER.")
+  (attr virtual)
+  (fp_text reference "" (at 0 0) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.15)))
+  )
+  (fp_text value "" (at 0 0) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.15)))
+  )
+  (pad 1 thru_hole rect (at -1.27 -3.81) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 2 thru_hole rect (at -1.27 -1.27) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 3 thru_hole rect (at -1.27 1.27) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 4 thru_hole rect (at -1.27 3.81) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 5 thru_hole rect (at 1.27 3.81) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 6 thru_hole rect (at 1.27 1.27) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 7 thru_hole rect (at 1.27 -1.27) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 8 thru_hole rect (at 1.27 -3.81) (size 1.50622 0) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+)

kicad/archive/fab.pretty/fab-2X05SMD.kicad_mod

+(module fab-2X05SMD (layer F.Cu) (tedit 5F70CDB2)
+  (attr smd)
+  (fp_text reference >NAME (at -0.889 -6.985) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value >VALUE (at -0.254 6.985) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (pad 1 smd rect (at -2.794 -5.08) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 2 smd rect (at 2.66446 -5.08) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 3 smd rect (at -2.794 -2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 4 smd rect (at 2.66446 -2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 5 smd rect (at -2.794 0) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 6 smd rect (at 2.66446 0) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 7 smd rect (at -2.794 2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 8 smd rect (at 2.66446 2.54) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 9 smd rect (at -2.794 5.08) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+  (pad 10 smd rect (at 2.66446 5.08) (size 2.54 1.27) (layers F.Cu F.Paste F.Mask))
+)

kicad/archive/fab.pretty/fab-3.5MMTERM.kicad_mod

+(module fab-3.5MMTERM (layer F.Cu) (tedit 200000)
+  (attr virtual)
+  (fp_text reference >NAME (at -0.17272 -4.36372 180) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.1016)))
+  )
+  (fp_text value "" (at 0 0) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.15)))
+  )
+  (fp_line (start -3.39852 -3.39852) (end -3.39852 2.19964) (layer B.SilkS) (width 0.127))
+  (fp_line (start -3.39852 2.19964) (end -3.39852 3.59918) (layer B.SilkS) (width 0.127))
+  (fp_line (start -3.39852 3.59918) (end 3.59918 3.59918) (layer B.SilkS) (width 0.127))
+  (fp_line (start 3.59918 3.59918) (end 3.59918 2.19964) (layer B.SilkS) (width 0.127))
+  (fp_line (start 3.59918 2.19964) (end 3.59918 -3.39852) (layer B.SilkS) (width 0.127))
+  (fp_line (start 3.59918 -3.39852) (end -3.39852 -3.39852) (layer B.SilkS) (width 0.127))
+  (fp_line (start -3.39852 2.19964) (end 3.59918 2.19964) (layer B.SilkS) (width 0.127))
+  (pad 1 thru_hole circle (at 1.79832 0) (size 2.18186 2.18186) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+  (pad 2 thru_hole circle (at -1.69926 0) (size 2.18186 2.18186) (drill 0.99822) (layers F&B.Cu F.Paste F.SilkS F.Mask))
+)